OrCAD X is the new integrated PCB design platform from Cadence. It enhances the PCB design process, making it faster, easier, and well-connected.
OrCAD enables engineers to address PCB design challenges at any stage:
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Individuals
Professionals, Small Businesses, and Teams
Professionals, Small Businesses, and Teams
AWR Interface
Multi-Style Design Creation (Tabular/Graphical/Language)
Allegro Design Entry (System Capture)
System Level Design (3 Boards)
System Level Design (Unlimited Boards)
Enable Access to Centralized Pulse
Audit Rules in Design Integrity
Variants Flow
MTBF Analysis
PCB Editor
Intelligent Topology Apply of Electrical Constraint Rule Set (ECSets)
PCB Interconnect Bundle, Flow Creation, Editing and Controls
Rigid Flex Design
PCB Design for Assembly, DFA Placement Matrix Rules
PCB Editor Floorprint Editor
Auto-interactive Breakout Technology
Auto Connect - Direct-to-Etch Auto Routing for Selected Clines
Dynamic Flow Creation
Auto-interactive Trunk Routing
Plan Spatial Feasibility Analysis and Feedback
Generate Topological Plan
Convert Topological Plan to Traces (CLINES)
Allegro RF PCB Aware Technology
MCAD/ECAD Incremental Design Data Exchange (EDMD)
New 3D Canvas
Embedded Packaged Components
Dynamic Fillet Glossing Option
AWR Microwave Office Interface
Layer Base Dynamic Shape Control
Vision (Routing, Placement)
Automatic Power Plane Generation 23.1
Dynamic Backdrilling
Allegro Router (High Performance Level)
Design for Manufacturing
Advanced Rules
Allegro PCB Router 256U
Allegro PCB Router 6U
High Speed Paramterized Structures
Intelligent, Navigatable PDF Output from PCB Editor
RouteVision
HDI Micro-via Stack Editing
Auto-interactive Delay Tuning (AiDT)
Auto-interactive Phase Tuning (AiPT)
TimingVision
DesignTrue DFM Rule Aggregator
DesignTrue DFM: In-design DFM, DFA: core Checks (100+ Checks)
DesignTrue DFM: In-design DFM, DFA: Flex Checks
DesignTrue DFM: In-design DFM: DFF, DFA and DFT Advance Checks (1000+ Checks)
Table Driven Constraints (Physical, Spacing, Electrical)
Special Routing (Tabbed, Weave, offset, Snake, Scribble, Coutour)
Generic GPU Acceleration
Electrical Rules (Reflection, Timing, Crosstalk)
Electrical Routing Rules: Impedances and Delay
Region-based Rules
Diff Pairs, Physical, Spacing, Properties, SameNet Rules Worksheet
RAVEL Checker
RAVEL Developer
Estimated Crosstalk Rules
Derived Constraint Rule Sets (Physical Spacing)
X:AI, JedAI, and Pulse Capable
LiveBOM
Backward Compatable to 17.2
Can access SamacSys and UltraLibrarian for parts